1. Field of the invention
The present invention relates to device and method for binary-multilevel logic operation, especially to the logic gates and their operational methods for processing multilevel logic and binary logic signals.
2. Description of the prior art
Most of modern electronic systems basically use digital signal processing, which processes electrical signals in digital forms. Digital signal processing refers to a method that processes, for a certain purpose, the digital data converted from analog signals through an A/D(Analog to Digital) converter and obtains desired results.
Generally, digital signals are represented by binary numbers and logic gates are widely used to perform logic operations between these binary numbers. Conventional logic gates are used only for the input of binary numbers.
The structure and operation of conventional gates will be described further herein below:
The truth table for a conventional binary OR gate is shown in FIG. 1. A symbol for such an OR gate is commonly expressed as an addition symbol. (+), while the present invention uses a different symbol of (=+=) indistinction from the arithmetic addition symbol (+). FIG. 2 represents a symbol for the conventional binary OR gate.
The binary OR gate truth table, shown in FIG. 1, represents relationship between the input and output of the binary OR gate shown in FIG. 2. In FIG. 2, if both inputs are at the level of logic 0, the output will be at the level of logic 0. If the inputs are logic 0 and logic 1 respectively, the output will be logic 1. And if both inputs are at the level of logic 1, the output will be at the level of logic 1.
FIG. 3 shows the truth table for a conventional binary AND gate. A symbol for such an AND gate is commonly expressed as (.cndot.) A symbol for the conventional AND gate is shown in FIG. 4.
The binary AND gate truth table, shown in FIG. 3, represents relationship between the input and output of the binary AND gate shown in FIG. 4. Namely, if both inputs are at the level of logic 0, the output will be at the level of 0. The inputs of logic 0 and logic 1 will result in the output of logic 0. The output will be logic 1 if both inputs are at the level of logic 1.
Additionally, FIG. 5 shows the truth table for a conventional binary EXCLUSIVE OR gate. A symbol for such an EXCLUSIVE OR gate is commonly expressed as (.sym.). A symbol for the conventional EXCLUSIVE OR gate is shown in FIG. 6.
The binary EXCLUSIVE OR gate truth table, shown in FIG. 5, represents the input and output of the binary EXCLUSIVE OR gate shown in FIG. 6. Namely, if both inputs are at the level of logic 0, the output be at the level of logic 0. The inputs of logic 0 and logic 1 will result in the output of logic 1. The output will be logic 0 if both inputs are at the level of logic 1. Here the logic 0 or logic 1 represents a logic value 0 or a logic value 1 and can be mapped into and used as an actual voltage level of 0 volt or 1 volt.
Accordingly, such binary OR, AND, and EXCLUSIVE OR gates are widely used for most of the digital signals that can be expressed in the columns of binary numbers.
In the meanwhile, a problem exists in determining how one can perform necessary operations for the case where one of either inputs, for such binary logic gates, have no binary logic values. The output of the binary logic gates explained earlier for processing binary logic values will also have binary values. But, after the operation of arithmetic addition or multiplication of the binary logic values, the binary logic values will be changed to multilevel logic values. To solve such a problematic operation for processing multilevel logic values and binary logic values, several binary logic gates can be used.
The configurations of the prior art for performing binary-multilevel logic operations using binary logic gates are shown in FIGS. 7 to 9.
The configuration of the prior art for performing an OR operation, for processing binary-multilevel signals, is shown in FIG. 7, the configuration of the prior art for performing an AND operation, for processing binary-multilevel signals, is shown in FIG. 8, and the configuration of the prior art for performing an EXCLUSIVE OR operation, for processing binary-multilevel signals, is also shown in FIG. 9.
As shown in FIG. 7, a conventional gate for processing binary-multilevel OR operations can not directly process multilevel logic values since it uses the binary logic OR gate. Therefore, binary-multilevel logic OR operations are performed by a circuit configuration, consisting of a plurality (K) of binary OR gates 1, where binary logic values are inputted from one common input point and plural binary logic values are inputted as a plurality (K) of binary logic values respectively from other individual input signals, and also of an arithmetic adder 2, where the outputs of a plurality (K) of said binary logic OR gates 1 are inputted to and performs their arithmetic additions.
Here, said arithmetic adder 2, which of course is designed to make multilevel logic signals, is realized as a full adder. In some cases an arithmetic multiplicator is used instead of said arithmetic adder.
As shown in FIG. 8, a conventional gate for processing binary-multilevel AND operations can not directly process multilevel logic values since it uses binary logic AND gates. Therefore, binary-multilevel logic AND operations are performed by a circuit configuration consisting of a plurality (K) of the binary AND gates 11, where binary logic values are inputted from one common input point and plural binary logic values are inputted as a plurality (K) of binary logic values respectively from other individual input signals, and an arithmetic adder 12, where the outputs of a plurality (K) of said binary logic OR gates 11 are inputted to and performs arithmetic multiplication.
Here, said arithmetic adder 12, which of course is designed to make multilevel logic signals, is realized as a full adder. In some cases an arithmetic multiplicator is used instead of said arithmetic adder.
As shown in FIG. 9, a conventional gate for processing binary-multilevel EXCLUSIVE OR operations can not directly process multilevel logic values since it uses binary logic EXCLUSIVE OR gates. Therefore, binary-multilevel logic EXCLUSIVE OR operations are performed by a circuit configuration, consisting of a plurality (K) of the binary EXCLUSIVE OR gates 21, where binary logic values are inputted from one common input point and plural binary logic values are inputted as a plurality (K) of binary logic values respectively from other individual input signals, and an arithmetic adder, where the outputs of a plurality (K) of said binary logic EXCLUSIVE OR gates 21 are inputted to and performs arithmetic multiplication.
Here, said arithmetic adder, which of course is designed to make multilevel value signals, is realized as a full adder. In some cases an arithmetic multiplicator can be used instead of said arithmetic adder.
However, since the same numbers of binary logic gates as the multilevel numbers are needed to perform binary-multilevel logic operations by utilizing the conventional binary logic gates aforementioned, there exists a problem that a circuit configuration, for electronic systems, can be too complicated to apply conventional method to the electronic systems.